Hello!,

I would like to use the 10/100 MAC in a TCP/IP project for an FPGA here.

But since I plan on NOT using a classic or RISC processor, but rather doing the
whole project in Verilog, it would be a much simpler interface to the
MAC if the following change were made:

Instead of "looping" on the *current* Rx/Tx Buffer Descriptor "Ready" bit,
what if the MAC looped through
ALL Tx and Rx buffer descriptors, and simply used the next one which was
"ready to go"? So in other words, if RxBDAddress is 13, and we are
looping on BD 13 waiting for the Ready bit, instead loop on ALL the Rx
BD's, waiting for any one of them to be ready.

There are several reasons why this would simplify my design, and eliminate a lot of buffer allocation logic.

So, would this be a straightforward change? It appears to me that it
would be done in eth_wishbone.v, but I have not yet completely investigated.

Does anyone have any advice on how to do this? If it's a terrible idea, and
will ruin my life, please let me know :-)

Thanks,
Chuck Heller
TAMS Inc

PS. Sorry if this is a duplicate message.